The present invention relates to the fabrication of semiconductor circuits and, in particular, to the fabrication of inductive elements with high quality factors (Q).
As the need for miniaturization of electronic circuits continues to increase, many digital and analog circuits, such as operational amplifiers and microprocessors, are successfully implemented in silicon-based integrated circuits (IC). These circuits typically include various types of diodes, active devices, such as field effect transistors (FET), and passive devices, such as resistors, capacitors and inductors.
Radio frequency (RF) circuits remain, however, a challenge to minituarization of electronic circuits. One of the obstacles posed by advanced RF circuits, which include cellular phones and wireless modem circuits, is the difficulty in fabricating a good inductor in silicon technologies which is suitable for RF applications. Currently, implementing high quality factor (Q) inductors that operate at high RF remains problematic to very large scale integration (VLSI) IC semiconductor chips. Attempts to integrate high Q inductors into the silicon technologies have typically yielded inductor Q values of less than five, mainly because silicon substrates, as opposed to gallium arsenide substrates, are conductive and, thus, they induce losses. Another problem is that high inductance values (L), which are a requirement for high RF circuits, necessitate a large silicon chip area. This requirement prevents miniaturization of such circuits. Further, physically voluminous RF circuits cannot operate at high frequencies, where the short wavelengths demand physically small components. Currently, there is a growing demand for increased efficiency, since high frequency operations are highly desirable for induction elements, since they permit a decrease in the size of the device while affording the same reactance.
Since Q is directly proportional to the inductance (L) and the resonant angular frequency of oscillation (xcfx89), and inversely proportional to the series loss of the inductor or the resistance (R), high Q designs strive to increase the inductance and decrease the resistance, while keeping parasitic capacitance to a minimum so that high oscillation frequencies can be achieved. Several techniques have been developed in the semiconductor industry but with limited results. For example, a known technique employs wide metal lines. Unfortunately, because both the inductor area and the parasitic capacitance are increased, the oscillation frequency decreases and, thus, the useful frequency range is limited.
Accordingly, there is a need for further downsizing of induction elements, such as inductive loops on ICs, operating at high RF frequencies with low losses and high efficiency. There is a need in the art for a high Q inductor that will only slightly influence other components of the circuit, that has a sufficiently high current capacity and high inductance, and that occupies a minimal substrate area. In addition, there is a need in the art for a process for fabricating such an inductor.
The present invention provides a method for fabricating a high Q inductor element. The present invention employs a micro-electro-mechanical-system (MEMS) structure, in the form of a silicon micro-fan structure, formed by deep etching of silicon with high aspect ratio and high precision etch profile control. A plurality of high Q inductors for RF circuit applications are formed over thin silicon walls of such MEMS structure. The silicon walls, which can be any support elements for the high Q inductors, provide mechanical stability to the inductor loops as well as low losses and reduced parasitic capacitance.
Additional advantages of the present invention will be apparent from the following detailed description of the invention, which is provided in conjunction with the accompanying drawings.